A Fabless Chip Design Center

Design Service Today.
Vietnamese Chips Tomorrow.

A fabless semiconductor design center with real in-house expertise across the full chip design lifecycle, from architecture to physical design.

EDA & Tooling Ecosystem We Build With
CadenceSynopsysSiemens EDAXilinxArmRISC-V

End-to-End IC Design Capability

Front-end through back-end IC design outsourcing for international fabless customers. End-to-end ownership from Specs → Architecture → RTL → Verification → FPGA → GDSII → Bring-up → System, backed by senior silicon architects with 25-30+ years across global semiconductor leaders. Our focus areas include AI infrastructure and high-performance computing, backed by decades of global engineering experience driving real technology transfer into Vietnam.

Physical Design & Sign-off (RTL2GDSII)

Full RTL2GDSII ownership at advanced nodes: TSMC 16/12/5nm and Samsung 5/4nm. Synthesis, DFT, P&R, MMMC STA, SI/PI, IR-drop, DRC/LVS, parasitic extraction through GDSII foundry handoff. IP hardening for ARM, RISC-V, LPDDR, and 3rd-party IPs.

4nm5nm12nmDFTGDSII

RTL Design

Verilog and SystemVerilog RTL coding, IP integration, and subsystem/SoC assembly. ARM & RISC-V control planes, custom AI/DSP accelerators, memory subsystems (DDR/LPDDR/HBM), and high-speed interconnects (PCIe, USB, MIPI, Ethernet).

SystemVerilogARMRISC-VSoC Assembly

Verification & Validation

SoC-level UVM verification with closed-loop Metric-Driven Verification (MDV), formal methods, and emulation-friendly flows. Proven first-silicon success across AI, automotive, communications, and storage SoCs.

UVMFormalMDVEmulation

Dedicated Engineering Teams

Scale your R&D with managed offshore design centers (ODC). Flexible engagement: project-based, SoW, staff augmentation, or long-term ODC, with secure IP practices and transparent KPIs.

ODCSoWStaff AugBOT

Process & Foundry Transitions

Porting existing IP and SoC designs to new process nodes or foundries. PDK migration, library re-characterization, flow re-tuning, and PPA recovery on advanced nodes.

TSMCSamsungPDK Migration

FPGA Feasibility & Prototyping

Feasibility, prototyping, and validation on UltraScale+, Zynq, Virtex, and Kintex platforms. Multi-FPGA architectures, PCIe-based hostless designs, high-speed ADC/DAC (JESD204B/C), Linux and FreeRTOS bring-up.

UltraScale+ZynqJESD204B/C

High-Speed PCB & Embedded

Complex 12-16 layer PCBs combining RF, digital, and high-speed signaling. Board design, layout, bring-up, and embedded software for chip validation and customer dev kits.

RF + DigitalHigh-SpeedBring-up

IP Benchmarking & Hardening

PPA evaluation and hardening of 3rd-party IPs or internal blocks. Independent comparison of cores, memory controllers, and interconnect IPs, informed selection before SoC integration.

PPAHardeningIP Selection

Microarchitecture

System and chip-level architectural exploration and feasibility. Workload-driven definition of compute, memory, interconnect, and I/O subsystems, defined before implementation begins.

SoC SpecFeasibilityPPA Targeting

Building Vietnamese Chips

Beyond services, QNSC is developing a proprietary chip portfolio targeting accessible categories where Vietnamese design talent can compete globally. Start with moderate-complexity products, accumulate IP, then expand.

IoT

IoT Chip

Ultra-low-power SoC with integrated connectivity for smart edge devices.

CoreARM Cortex-M + RF subsystem
Process28-55 nm (low-power)
ConnectivityBLE, Wi-Fi, LoRa (TBD)
PowerUltra-low standby, energy harvesting

Market: Smart home, agritech, asset tracking

MCU

Microcontroller

General-purpose MCU for industrial control, home appliances, and entry-level automotive applications.

CoreARM Cortex-M0 / M3 / M4
Process40-90 nm
PeripheralsGPIO, UART, SPI, I²C, ADC
MemoryEmbedded Flash + SRAM

Market: Industrial control, home appliances

SE

Smart Card / Secure Element

Security-certified chip for smart cards, eSIM, payment, and identity applications.

CoreSecure CPU + crypto accelerator
Process90-180 nm (security-grade)
CryptoAES, RSA, ECC, SHA
Cert. roadmapCommon Criteria / EMVCo

Market: Smart cards, eSIM, payment, identity

Quy Nhon, Vietnam, coastal city with mountains

Vietnam's Rising
Semiconductor City

Quy Nhon is the administrative center of Vietnam's new Gia Lai province (post-2025 provincial merger), a coastal hub anchored by strong engineering universities, active provincial government support for the semiconductor industry, and an exceptional quality of life for engineers.

QNSC is built on a direct partnership with Quy Nhon University (QNU), one of the few Vietnamese universities offering an official semiconductor program, guaranteeing a sustained pipeline of trained junior engineers feeding our OJT Sub Team and long-term scale-up.

Active Gia Lai provincial government support
Strategic partnership with Quy Nhon University (QNU)
Official semiconductor program, rare in Vietnam
Guaranteed junior engineer talent pipeline
Node in Vietnam's national semiconductor strategy
Lower cost of operations · high engineer retention
Coastal lifestyle · direct flights to Hanoi & HCMC
Read "Why Quy Nhơn? Why Vietnam?", a letter from our Executive Board Advisor

Built by Industry Veterans

QNSC is led by Vietnamese founders with deep entrepreneurial and engineering experience, supported by an Executive Board Advisor and Strategic Advisors bringing 25-40+ years of leadership across global semiconductor and AI infrastructure companies: IBM, Meta, Intel, Samsung, TSMC, Arm, Synopsys, Qualcomm, Bosch, Ericsson.

Leadership

Vũ Hồng Quân

Vũ Hồng Quân

Chairman & Co-Founder

Vietnamese industrial entrepreneur and technology investor. Chairman & Co-Founder of QNSC and founder/chairman of multiple industrial companies across construction materials, mining, manufacturing, and Vietnam-Japan export ventures, including TAKUMINO Co. (JV with Japan's OKUNO Trading), My Quang JSC, and An Vien An Loc Phat Investment. Actively involved in semiconductor, AI, advanced manufacturing, and technology commercialization initiatives in Vietnam.

  • Board Member, PISICO Bình Định Corporation
  • Vice Chairman, Vietnam Young Entrepreneurs Association (Central)
  • Chairman, Young Entrepreneurs Association of Gia Lai Province
  • Member, Central Committee of the Vietnam Fatherland Front (2024-2029)
  • BBA, Auckland University of Technology (AUT), New Zealand
QL

Quang Lê

CEO & Co-Founder

Founding CEO of QNSC. 15+ years of P&L leadership across large engineering organizations in the US, EU, and Asia-Pacific. Deep expertise in AI-augmented engineering management: shaping engineering strategy, aligning delivery with customer business outcomes, and integrating AI across the full engineering lifecycle at scale, directly applicable to modern AI-accelerated chip design flows.

  • AI adoption strategy across full engineering lifecycle
  • Built next-generation leadership programs aligned with business strategy
  • PMI Agile Certified Practitioner (PMI-ACP) · Professional Scrum Master I & II
  • MSc Business Administration (Leadership & Management), Deakin University, Australia
  • MSc Information System (Data & Analytics), Deakin University

Executive Board Advisor

Nguyễn An Thạo
Executive Board Advisor

Nguyễn An Thạo (Thao An Nguyen)

Semiconductor · AI Infrastructure · Hardware at Hyperscale

Thao Nguyen is a Vietnamese-American technology entrepreneur with 40 years of leadership experience in semiconductor design, data center infrastructure, and large-scale system architecture. He began his career as a VLSI chip designer at IBM in 1985 and later played a key role at Facebook through the Open Compute Project, contributing to the design and deployment of millions of servers for hyperscale data centers worldwide. Today, he leads memory-centric AI infrastructure innovation as Founder & CEO of TORmem Inc. (USA).

As an overseas Vietnamese, Thao is passionate about helping Vietnam grow its high-tech and semiconductor industry by transferring real-world knowledge, engineering expertise, and global industry experience to the next generation of Vietnamese engineers and technology leaders.

40yr
Silicon & Hardware Leadership
8+
US Patents Held
M+
Servers Deployed (Open Compute)
1985
IBM VLSI · Career Start
Career: IBM (VLSI design) · Facebook/Meta (Open Compute) · NetApp · Equinix · Founder & CEO, TORmem Inc. Expertise: PCIe Gen7, RDMA, CXL, AI hardware, ASIC design, memory-disaggregated architectures Education: BSEE, MSEE · CTO Program, Cornell University, USA

Strategic Advisors & Experts

Dr. Afzal Khan

Dr. Afzal Khan

SoC Architecture
  • 30+ years Specs-to-System SoC & IP product design
  • Deep AI architecture leadership: NPU, GPU, DSP, ISP, secure compute
  • Chip Lead on advanced AI Vision Processor SoC (ARM & RISC-V control planes)
  • PhD Computer Architecture & Information Security; BS, MSEE Arizona State University
Jafar Safdar

Jafar Safdar

Chip Design & Operations
  • 31+ years in semiconductor industry across product, sales, application engineering
  • Founded/co-founded 3 chip design startups; raised $12M+ funding
  • Led physical design tape-outs at TSMC 5/7nm and Samsung 4/5nm with Intel, Qualcomm, Samsung
  • Key contributor to Synopsys product line scaling to $400M annual revenue
  • MSEE, California State University Northridge, USA
Shahid Mustafa

Shahid Mustafa

Finance & Corporate Strategy
  • 29+ years in banking, fintech & digital finance leadership
  • Co-founder Telenor Microfinance Bank; co-creator of easypaisa (Pakistan's largest fintech)
  • Secured 45% strategic investment from ANT Financial; scaled business 10× post-deal
  • Founding CEO, Pakistan Microfinance Investment Company
  • MBA LUMS · BSEE UET Lahore
Shahid Rizwan

Shahid Rizwan

Verification & SoC Strategy
  • 25+ years in ASIC Design & Verification
  • SoC-level verification at Arm (AI SoC), Intel (NoC), Ericsson, Bosch, ST, Toshiba
  • UVM, formal, MDV, PCIe/DDR/HBM, safety-critical & automotive SoCs
  • MSEE KAIST (Gold Medalist), South Korea

Two Tracks. One Team.

QNSC is building its workforce on two complementary tracks: experienced engineers driving delivery from day one, plus a Quy Nhon-based junior pipeline trained by senior silicon experts. The future scale engine of Vietnamese chip design.

Core Team

Senior Engineering Core

  • Team of 15 senior engineers anchoring delivery
  • 3-5+ years of hands-on production silicon experience
  • Direct hires from established semiconductor companies
  • End-to-end coverage: RTL · Verification · Physical Design · DFT
OJT Sub Team

Quy Nhon Talent Pipeline

  • Fresh graduates from Quy Nhon University and partner programs
  • Trained on real RISC-V, Arm, and AMBA chip design projects
  • 6-month immersive curriculum led by senior silicon experts
  • Production-ready engineers, the long-term scale engine of QNSC

Build the Future of
Vietnamese Semiconductors

We're hiring on both tracks: experienced engineers ready to deliver from day one, and new graduates ready to learn through our silicon expert-led OJT program.

For Experienced Engineers
  • RTL Design Engineer (3-5 yrs)
  • Verification Engineer (UVM / Formal)
  • Physical Design Engineer (PnR / Sign-off)
  • DFT Engineer
For New Graduates · OJT Track
  • Junior IC Design Trainee, Quy Nhon
  • 6-month silicon expert-led training program
  • Live and work in Quy Nhon
  • Path to permanent engineer role
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Contact Information

Office Address
Floor 1, Pisico Building, 99 Tay Son Street, Quy Nhon Nam Ward, Gia Lai Province, Vietnam
Email
contact@qnsc.vn
Phone
+84 779 446 268